1. Filed
One or more embodiments relate to a one-time-programmable non-volatile memory device, and more particularly relates to a programmable non-volatile memory device, including a transistor acting as an anti-fuse and two diodes for access.
2. Related Art
Korea Patent Publication 10-2001-0056831 relates to a method of making an anti-fuse of the semiconductor device, and more particularly relates to a method of making an anti-fuse of the semiconductor device using a right-angled corner of the semiconductor substrate to cause the breakdown of the insulator layer at a lower voltage, wherein the method of making an anti-fuse of the semiconductor device comprises: a step making right-angled corners by forming regular pattern on the semiconductor substrate that finished front end process; a further step depositing the gate oxide layer then stacking nitride layer and the first poly-silicon layer on top of the gate oxide layer; a further step forming a photo-resist pattern to expose the first poly-silicon layer at the right-angled corner of the semiconductor substrate; a further step exposing primarily the nitride layer at the right-angled corner of the semiconductor substrate by dry-etching the exposed first poly-silicon layer; a further step dry-etching the nitride layer; a further step depositing/patterning the second poly-silicon layer.
Korea Patent Publication 10-1997-0067848 relates to a semiconductor memory device and to methods for its fabrication, wherein the memory device improves the processing speed of the semiconductor memory device owing to consistent charge supply to the storage node capacitor because it comprises: an access transistor T to access the word line information, a storage node capacitor C to store the information at the access transistor T through the bit line, and a chare-up transistor P to supply charges to the storage node capacitor.
By the way, the non-volatile semiconductor memory is a semiconductor memory that can keep the information stored in the memory cell without power supply.
Such one-time-programmable non-volatile memory devices are electrically programmed, wherein the data storage principle of the memory device is to use a resistive path formed by applying a high programming voltage across the gate oxide layer to cause the gate breakdown.
According to a prior art, FIG. 1 illustrates the cross-section of the storage n-channel MOS transistor 990. As illustrated in FIG. 1, it is a typical n-channel MOS transistor includes: a thin oxide layer 935, a poly-silicon gate 940 on top of the oxide layer, sidewall spacers 925 formed on the side of the gate, source region 926 and drain region 927 doped with high and low concentration in n-type separated by the gate 940 in between, a semiconductor substrate 915 doped with low concentration in p-type. The basic principle of programming is to connect the gate 940 of the storage n-channel MOS transistor 990 to the ground GND at 0V and to apply a high voltage either to the source region 926 or drain region 927 to cause the gate breakdown at the oxide layer making a resistive path. Therefore, a high voltage needed to be applied to the source region 926 or drain region 927 to access MOS transistor. As the paths that the gate breakdown occur, a resistive path 936 formed on the oxide layer 935 between the gate 940 and source region 926; and another resistive path 937 formed on the oxide layer 935 between the gate 940 and drain region 927 are illustrated in thick lines to help understanding. It is a disadvantage that a thick oxide layer MOS transistor is needed in the access MOS transistor to be suitable for high voltage operation while a thin oxide layer MOS transistor is used in the storage MOS transistor 990. It is also a disadvantage that the need of the access transistor is the fundamental limitation in increase of the integration density.
According to an aspect of the prior art, FIG. 2 illustrates the circuit diagram about a memory cell 910 including two access n-channel MOS transistors and one storage n-channel MOS transistor. As illustrated in FIG. 2, the gate of the storage n-channel MOS transistor 900 is grounded to the ground GND at 0V; the gates of each access n-channel MOS transistor 901, 902 are connected to each word lines WL0, WL1; the drains of each access n-channel MOS transistor 901, 902 are connected to the common bit line BL; the sources of each access n-channel MOS transistor 901, 902 are connected to the source 956 and drain 957 of the storage n-channel MOS transistor 900 respectively.
As described previously, the device includes the access transistors and it is the fundamental limitation in increase of the integration density.
As described previously, the high voltage should be transferred through the access n-channel MOS transistors 901, 902 to apply the high voltage for programming to the source 956 or drain 957 of the storage n-channel MOS transistor 900. Therefore, a high voltage should be applied to the common bit line BL and a higher voltage should be applied to the selected word line WL0 or WL1.
According to the prior art, the fabrication process becomes relatively complicated because the memory cell should be fabricated in high density MOS transistors with two different oxide layer thicknesses. Further, three transistors are required to make a two-bit storable memory cell, being the fundamental limitation in increase of the integration density.